Figure 5.2. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: timing diagram illustrating the relation between the data signal (D), the clock signal (CP), and the control signals (S105 i S106).

Figure 5.3. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: one possible realization of the block diagram shown in Figure 5.1, using only the standard cells shown in Figure 4.7. Each standard cell has two numbers associated with it. The first number (2929, 8940, etc…) refers to the standard cell part number (as defined by the designer of the standard cell family), while the second number (1, 2, etc…) refers to the original number of the standard cell in the diagram (as defined by the designer of the diagram).

* A simple FSK modulator for voice-band data modems.

* Implemented with the RCA CMOS/SOS standard cell family.

* Author: Salim Lakhani.

* Column numbers:

* 09 17 25 33 41 49 57 65 73

* Pin numbers:

* 1 2 3 4 5 6 7 8

S8940 1P1 1P2 FQ 1

S8940 2P1 2P2 S103 2

S9040 3P1 S105 3

S1620 2P1 28P8 4P3 4

S2920 5P4 1P1 5P3 5P4 5

S1620 8P4 7P4 6P3 6

S2920 6P3 1P1 7P3 7P4 7

S2920 7P3 1P1 8P3 8P4 8

NEXT 11

S1500 11P1 3P1 11

S1500 12P1 3P1 12

S1340 13P1 5P3 4P3 DUMMY 8P3 13

S1620 13P1 11P1 14P3 14

NEXT 24

S2130 24P5 14P3 11P1 DUMMY 24P5 DUMMY DUMMY 24P8 24

S2130 25P5 24P5 11P1 DUMMY 25P5 DUMMY DUMMY 25P8 25

S2130 26P5 25P5 12P1 DUMMY 26P5 DUMMY DUMMY 26P8 26

S2130 27P5 26P5 12P1 DUMMY 27P5 DUMMY DUMMY 27P8 27

S2130 12P1 27P8 12P1 DUMMY 28P5 DUMMY DUMMY 28P8 28

S8800 14P3 FSKOUT 29

S8800 28P8 S106 30

Figure 5.4. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: the file connect.dat. It contains the diagram from Figure 5.3, formatted according to the rules set forth in the CADDAS manual. One standard cell has one line assigned to it. The first column contains the part number of the standard cell. The last column contains the ordinal number of the standard cell in the diagram. Other columns (between the first and the last) define the connections between the standard cells (details are given in the text).

1	10	15	20	25	30	35	40	45	50
CTRL		1			1	1	1
SPEC	1000

Figure 5.5. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: the file lmode.dat. The valid options in the control line (CTRL) are as follows: (a) column 10, COMPARE option—the optional file compare.dat has to exist; (b) column 15, PRINT option—the mandatory print.dat file specifies which signals will be printed out; otherwise, all the signal generator outputs, as well as all the standard cell outputs, will be printed out; (c) column 20, SPIKE option—if this option is selected, the appropriate warning message will be printed out, if a short irregular signal appears during the simulation; (d) column 30, CONNECTIVITY option—all the output loads for the standard cells and the signal generators will be printed out, which matters in the cases when the output loads affect the timing of the signals; (e) column 35, OVERRIDE INITIAL CONDITION option—the simulation will be performed even if the desired output state of the outputs cannot be effected during the initialization; (f) column 40, CONSISTENCY BYPASS option—the simulation will continue even if the inconsistency of the output values of the standard cells is detected; (g) column 50, COMPRESS option—normally, a new line is output whenever the input or the output of any standard cell changes; if this option is selected, a new line is output only when one of the signals from the print.dat file changes. The second control line (SPEC) is the place to specify the desired simulation time.

GENF FQ 0 250 0 4 10

GEN S103 0 500 1

GEN S105 0 50 1 500 0 550 1

Figure 5.6. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: the contents of the gen4.dat file. For the periodic signals (GENF), one must assume the following: (a) the first of the five specifiers refers to the logic level at the beginning of the simulation; (b) the second specifier refers to the number of periods in the waveform that is being specified in the GENF line; (c) the third specifier refers to the time index of the first logic level change, meaning that the periodic behavior starts at that time; (d) the fourth specifier refers to the length of the interval during which the value specified in the fifth specifier lasts, expressed through the number of the simulation intervals; (e) the fifth specifier defines the logical sequence that repeats itself. For example, GENF GORAN 0 2 100 50 10 specifies a periodic signal, named GORAN, with the initial value of 0; at time index 100, a positive transition occurs; at time index 150, a negative transition occurs; and at time index 200, another positive transition occurs, and that is the end of the first of the two periods. At time index 250, a negative transition occurs again, lasts until the time index 300, where the second period ends, and stays that way until the end of the simulation (if the simulation still runs after the time index 300). The following rules apply to aperiodic signals (GEN): (a) the first specifier defines the initial logic level, at time index 0 (that is, at the beginning of the simulation); (b) the second specifier defines the time index of the first transition, etc…. The total number of the specifiers in the GEN line is , where N stands for the total number of signal changes. For example, GEN MILAN 0 50 100 specifies an aperiodic signal named MILAN, with the following characteristics: initial value is equal to 0, the first positive transition occurs at time index 50, the first negative transition occurs at time index 100, and the value of 1 remains through the rest of the simulation.

1	5	10	15	20	25
POSPNT			1	25
SLOT			0000		1000

1	8	18	28	38	48	58	68
PNT	FQ	SKIP	SKIP	5P3	SKIP	SKIP
PNT	8P3	SKIP	SKIP	13P1	SKIP	SKIP
PNT	SKIP	S103	SKIP	SKIP	S105	SKIP
PNT	SKIP	SKIP	S106	SKIP	SKIP	SKIP
PNT	FSKOUT

Figure 5.7. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: contents of the print.dat file. The reader should notice that the parts (a) and (b) refer to the fragments of the same file. The fields in the POSPNT line are as follows: (a) columns 13–15 specify the number of windows through which the signals are being monitored; (b) columns 18–20 specify the number of columns in the printout; (c) column 25 specifies the type of printout, with zeros and ones (if nothing is specified), or with L and H (if the column 25 contains the symbol H). The fields in the SLOT line refer to the beginning and end of the window through which the simulation is being monitored (two fields for the specification of one window, 2N fields for the specification of N windows). The PNT lines specify either the signals to be monitored (if their names are given, corresponding to the columns in the printout), or empty columns (if the SKIP keyword is specified).

INIT 5P4 0 (* D-FF #5: loop definition *)

INIT 5P3 1 (* D-FF #5: consistency definition *)

INIT 7P4 0 (* D-FF #7: loop definition *)

INIT 7P3 1 (* D-FF #7: consistency definition *)

INIT 8P4 0 (* D-FF #8: loop definition *)

INIT 8P3 1 (* D-FF #8: consistency definition *)

Figure 5.8. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: the contents of the capinit.dat file. The first INIT line specifies that the initial value of the 5P4 signal is zero, and so on. Beside the INIT lines, this file can contain the CAP and the CAPA lines as well. The CAP lines provide users with capability to completely ignore the capacitance computations, which are performed by the translator. The CAPA lines provide users with capability to specify the capacitances to be added, when the translator computes the capacitances in the system.

An FSK modulator for the voice-band data modem

Figure 5.9. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: contents of the title.dat file. This file contains one line with at most 40 characters. That line appears on every page of the printouts of the logic and timing simulations.

GUIDELINES FOR LOGSIM-BASED TESTING OF A DIGITAL (PROCESSOR) MODULE IN DARPA-SPONSORED PROJECTS
(created: May 4, 1985)

1) Assuming that the module is designed using only the cells of the chosen standard cell family, one has first to fully comprehend the logic of the module.

2) A set of input and output test vectors has to be carefully prepared (on paper, off-line). Also, the delay information which specifies how much will different outputs lag behind different inputs (this is of special importance for the later creation of the compare.dat file). The methodology of "divide-and-conquer" works well here. It is suggested that the entire work (which defines exhaustive testing) is created as a set of small testing experiments. Each of the small experiments should be precisely defined and documented.

3) Create the connect.dat file. This should be straight-forward, but time consuming, and error prone.

4) Create the capinit.dat file. Both loops and consistencies have to be defined by this file. This should be easy.

5) Create the print.dat file. This one should be easy. It defines how many signals in total have to be tested, which ones will that be, and for how many clock periods will the print-out go.

6) Create the lmode.dat file. This one should also be easy. It specifies how many clock periods will the simulation go, if the printout will be normal or condensed, and other options.

7) Create the gen4.dat file. This one represents your "wish lists" of input test vectors. Since "wish lists" are easy to make—this task will be easy (except that you have to carefully include all possible input cases). The related thinking was done during the task #2. Create a separate gen4.dat file for each of your experiments.

8) Create the compare.dat file. This one represents the "expected" values of output test vectors. Since all related thinking was done during task #2, this work should be nothing else but careful translation of concepts from task #2 into the format of the compare.dat file. This format should coincide with the format given in the print.dat file (only for signals to be compared). Please, remember the important role of both the logic and the gate delays (see the comment in task #2). Remember that the number of compare.dat files has to be the same as the number of gen4.dat files.

9) Double check all your work, on paper, before you start the simulation. This will save you lots of frustration.

10) Run the simulator program, once for each gen4.dat/compare.dat pair. Hopefully, each time the output file lprt.lst will contain no error messages (related to differences between compare.dat and the LOGSIM-generated output test vectors).

11) If everything was correct, please document all your work before the results fade away from your head.

12) If something is wrong, then you have the opportunity to learn that the real-life design is an iterative process. If something is wrong, that may mean one or more of the following:

A. Bug(s) in the logic.

B. Logic correct, but connect.dat file contains error(s).

C. Logic correct, but other LOGSIM files contain error(s).

D. Logic correct, but compare.dat file contains error(s).

Don’t panic! Just cool-down and re-check the logic diagram, connect.dat file, compare.dat file, and other input files, in a well structured manner.

12) Remember, the worst thing that can happen is that your documentation (task #10) claims that everything is OK, but the fabricated chip happens not to work. Note that RCA "guarantees" that if LOGSIM reports no timing errors, MP2D will create the mask which works, on condition that the design contains no logic errors. The LOGSIM and MP2D are responsible for timing errors; the designer(s) is(are) responsible for logic errors!

Figure 5.10. A guide for the LOGSIM program, based on the author’s experience (original version, developed 5/4/85).

Figure 5.11. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: block diagram of the final project, after all the changes pointed to by the LOGSIM program were entered.

Figure 5.12. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: detailed diagram of the final project from Figure 5.11, realized exclusively using the standard cells from Figure 4.7.

* A simple FSK modulator for voice-band data modems.

* Implemented with the RCA’s 3 m m single level metal CMOS/SOS standard cell family.

* Author: Aleksandar Purkoviæ.

* Column numbers:

* 09 17 25 33 41 49 57 65 73

* Pin numbers:

* 1 2 3 4 5 6 7 8

S8940 1P1 1P2 FQ 1

S8940 2P1 2P2 S103 2

S9040 3P1 S105 3

S1620 2P1 28P8 4P3 4

S2920 5P4 1P1 5P3 5P4 5

S1620 8P4 7P4 6P3 6

S2920 6P3 1P1 7P3 7P4 7

S2920 7P3 1P1 8P3 8P4 8

S1500 9P1 3P1 9

S1500 10P1 3P1 10

S1500 11P1 3P1 11

S1500 12P1 3P1 12

S1340 13P1 5P3 4P3 DUMMY 8P3 13

S2130 14P5 13P1 9P1 DUMMY 14P5 DUMMY DUMMY 14P8 14

S2130 15P5 14P5 9P1 DUMMY 15P5 DUMMY DUMMY 15P8 15

S2130 16P5 15P5 9P1 DUMMY 16P5 DUMMY DUMMY 16P8 16

S2130 17P5 16P5 9P1 DUMMY 17P5 DUMMY DUMMY 17P8 17

S2130 18P5 17P5 10P1 DUMMY 18P5 DUMMY DUMMY 18P8 18

S2130 19P5 18P5 10P1 DUMMY 19P5 DUMMY DUMMY 19P8 19

S2130 20P5 19P5 10P1 DUMMY 20P5 DUMMY DUMMY 20P8 20

S2130 21P5 20P5 10P1 DUMMY 21P5 DUMMY DUMMY 21P8 21

S2130 22P5 21P5 11P1 DUMMY 22P5 DUMMY DUMMY 22P8 22

S2130 23P5 22P5 11P1 DUMMY 23P5 DUMMY DUMMY 23P8 23

S2130 24P5 23P5 11P1 DUMMY 24P5 DUMMY DUMMY 24P8 24

S2130 25P5 24P5 11P1 DUMMY 25P5 DUMMY DUMMY 25P8 25

S2130 26P5 25P5 12P1 DUMMY 26P5 DUMMY DUMMY 26P8 26

S2130 27P5 26P5 12P1 DUMMY 27P5 DUMMY DUMMY 27P8 27

S2130 12P1 27P8 12P1 DUMMY 28P5 DUMMY DUMMY 28P8 28

S8800 22P8 FSKOUT 29

S8800 28P8 S106 30

Figure 5.13. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: net-list (for the final project) that corresponds to the detailed diagram shown in Figure 5.12.


Column number of the rightmost digit in the field	12	16	28

	7777	7	1

Figure 5.14. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: contents of the mmode.dat file: (a) a field that spans columns 9–12 refers to the identification number of the chip that is being designed; (b) a field that spans columns 13–16 refers to the technology that will be used during the fabrication; (c) a field that occupies the column 28 specifies whether the DOMAIN PLACEMENT option will (³ 1) or will not (0) be used. This option is explained in the text.

Figure 5.15. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: contents of the dmode.dat file. This file contains the user’s "wish list" in the domain of placement and routing, which the MP2D program must respect. In this case, the file is empty (40 blanks), meaning the user does not have any special requests about placement and routing, so the MP2D program will perform the entire placement and routing in the default manner.

DUMMY

1P2

2P2

14P8

15P8

16P8

17P8

18P8

19P8

20P8

21P8

23P8

24P8

25P8

26P8

28P8

FSKOUT

S106

Figure 5.16. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: contents of the drop.dat file. This file contains the list of signals to be ignored during the placement and routing process; the first signal is ignored, because it is physically nonexistent for historical reasons (DUMMY), and the remaining signals are ignored because they physically exist, but are unused ("hanging" signals).

An FSK modulator for the voice-band data modem

Figure 5.17. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: contents of the title.dat file. This file can be used with the LOGSIM program, as well as with the MP2D program. In this particular case, the designer has decided to have the same title.dat file for both programs (although he/she did not have to do it that way).

Figure 5.18. AN EXAMPLE FOR THE PRACTICAL WORK USING THE SC VLSI METHODOLOGY: a typical layout of the artwork file, formed by the MP2D program. The standard cells are laid in columns of the same height, and approximately same width. The standard cells are connected through the channels whose height depends on the number of connections to be made. The chip ID is directly ported from the mmode.dat file, shown in Figure 5.14.