Figure 6.27. Code optimization scheme #3, according to the Gross-Hennessy algorithm. The lines with arrowheads and single dash show the possible branch direction. The lines with arrowheads and double dashes show the code relocation. The hatched block stands for the initial position of the block that will be relocated. The crosshatched block stands for the space which is initially left blank by the code generator (i.e., it contains the nop instructions). is the basic block that is being optimized.

Figure 6.28. An example of the code optimization based on the Gross-Hennessy algorithm, for the SU-MIPS processor: (a) the situation after the code generation; (b) the situation after the code optimization. The details of the SU-MIPS assembly language can be found in the reference [GilGro83].

Figure 6.29. An example which shows the effects of register allocation on the code optimization: (a) an inadequate register allocation can decrease the probability of efficient code optimization; (b) an adequate register allocation can increase the probability of efficient code optimization. The details of the SU-MIPS assembly language can be found in the reference [GilGro83].

Figure 6.30. Two alternative methods of code generation for the loops in high-level languages: (a) the condition testing is performed at the top; (b) the condition testing is performed at the bottom.

For details see :D.Tabak. "High-Performance RISC Systems,"

Micropocessors and Microsystems, Vol. 13., No. 6., 1989.

Advanced RISC Microprocessors

Digital Equipment Corporation.

The first product realizing the Alpha AXP architecture is labeled 21064.

The Alpha is a 64-bit RISC-type microprocessor.

The first PowerPC implementation is the PowerPC 601 microprocessor

(also called MPC 601 by Motorola, and PPC 601 by IBM).

The name SPARC stands for scalable processor architecture.

The SPARC architecture follows the Berkley RISC design philosophy.

The MIPS acronym stands for

microprocessor without interlocked pipeline stages.

The MIPS system originated at Stanford University in the early eighties.

They were followed recently by the new generation RISC MC88110,

which is also a two-issue superscalar.

across technologies, cost rangers, performance rangers,

and to provide price-performance advantages.

TABLE 1. RISC Systems Technology

m = micron; x L = x-layer metal (x = 2,3,4); Frequency (MHz);

PGA = pin grid array.

* Dec Alpha and R4400 are 64-bit systems, all others are 32-bit systems.

** The R4400 external frequency is 75 MHz;

                internal pipeline frequency is double: 150 MHz.

TABLE 2. RISC Systems Architecture

IU = integer unit; FPU = floating-point unit; VA = virtual address;

PA = physical address.

* Can also be used as a 16 x 64 register file.

TABLE 3. RISC Systems ILP Features

ILP = instruction level parallelism; BPU = branch processing unit;

IU = integer unit; FPU = floating-point unit; GU = graphics unit;

* superpipelined, all others are superscalar.

** The IU and BPU.

TABLE 4.1 RISC Systems Memory Organization

Icache = on-chip instruction cache; Dcache = on-chip data cache;

Ecache = off-chip external cache.

TABLE 4.2 RISC Systems Memory Organization

TLB = Translation lookaside buffer.