Stage

Figure 6.16. The SU-MIPS processor: pipeline organization.

IF — Instruction Fetch and Program Counter increment;

ID — Instruction Decode;

OD — Computation of the effective address for load/store, or computation of the new value of Program Counter in the case of branch instructions, or ALU operation for arithmetic and logical instructions (Operand Decode);

SX — Operand read for store, or compare for branch instructions, or ALU operation for arithmetic and logic instructions (Store/Execute);

OF — Operand Fetch (for load).

Figure 6.17. Instruction formats of the SU-MIPS processor: alu.2 and alu.3 refer to the activities in the OD and SX stages of the pipeline. Instruction mnemonics and operand fields are outlined as in the original literature.

SOFTWARE-IMPOSED PIPELINE INTERLOCK

REORGANIZER:

#1 Rearranging the code sequence

(avoiding the interlocks and filling in the branch delays)

#2 If above is not possible, inserting the NOOPs

#3 Packing, if possible

#4 Assembly process

Figure 6.18. Evaluation of the SU-MIPS instruction set: performance data for the eight standard benchmark programs that were formulated at the Stanford University, at the request of DARPA, for the evaluation of various RISC processors.

Figure 6.19. An example of resource hazard. Symbol MLTP refers to the hardware multiplier (this is just one possible example).

Figure 6.20. An example of the DS (destination-source) timing hazard: an arrow pointing downwards stands for register write; an arrow pointing upwards stands for register read.

Figure 6.21. An example of the DD (destination-destination) timing hazard: an arrow pointing downwards stands for register write; an arrow pointing upwards stands for register read.

Figure 6.22. An example of the SD (source-destination) timing hazard: an arrow pointing downwards stands for register write; an arrow pointing upwards stands for register read.

Figure 6.23. Sequencing hazards in the SU-MIPS processor: the length of the delayed branch for various instruction types. Symbol n stands for the number of instructions (after the branch instruction) which are executed unconditionally.

Figure 6.24. Timing hazards in the SU-MIPS processor: , , —nominal (primary) instructions; , , —packed (secondary) instructions; , , , , —five stage pipeline for the instruction i; , , —decoding phases for the instructions A, B, C; , , , , , —execution phases for the instructions A, B, C.

Figure 6.25. Code optimization scheme #1, according to the Gross-Hennessy algorithm. The lines with arrowheads and single dash show the possible branch directions, forward or backward. The line with arrowhead and double dash shows the method of the code relocation. The hatched block stands for the initial position of the code that is to be relocated. The crosshatched block stands for the space initially filled, using the nop instructions, by the code generator. is the basic bloc that is being optimized.

Figure 6.26. Code optimization scheme #2, according to the Gross-Hennessy algorithm. The lines with arrowheads and single dash show the possible branch direction, before the code optimization (solid line), and after the code optimization (dotted line). The line with arrowhead and double dash shows the method of code duplication. The hatched blocks stand for the initial code positions, before the duplication. The crosshatched blocks stand for the space initially filled, using the nop instructions, by the code generator. is the basic block that is being optimized.