INSTRUCTION FORMAT

Figure 6.9. Instruction format of the UCB-RISC: DEST—destination; SCC—bit that determines whether the DEST field is treated as a destination register () or as a condition code (cond); , —source registers; imm13, imm19—immediate data—13 or 19 bits.

Instruction decoding and field extraction:

      ONLY 2% (10%) of the CHIP AREA!

      Register-to-register 3-operand instructions:

      Avialable operations:

       INTEGER ADD (w/wout CARRY)

       INTEGER SUB (w/wout CARRY)

       INTEGER INVERSE SUB (w/wout CARRY)

       BOOLEAN AND, OR, & XOR

      No suppport for:

      SHIFT AL

       ROTATE

      Why?

       NOT SUPPORTED BY HLL

       SYNTHESIZING OTHER INSTRUCTIONS

Figure 6.10. Activities related to the execution of the load instruction: (a) data in memory; (b) register state after load; (c) interpretation of immediate data (except ldhi); (d) interpretation of immediate data by the ldhi instruction, realized in the manner that enables straightforward forming of the immediate operand, using the logical OR (or some other logical function); (e) data in register after the load instruction.

b)

Figure 6.11. The store instruction related activities: (a) store instructions for variable size data: stw (store word), sth (store half-word) i stb (store byte); (b) memory write cycle for the stb instruction.

      SYNTHESIZING OTHER ADDRESSING MODES:

ALSO, PC-RELATIVE MODE:

            Effective_address = PC + imm

       Saving/restoring the registers.

       Passing the parameters.

       The RISC(y) solution:

       Multiple banks of registers (138).

       Only one bank is visible at a time (32).

Figure 6.12. Organization of a single register window (bank) in the register file with partially overlapping windows (banks), in the case of the UCB-RISC processor: HIGH—the area through which the data is transferred into the procedure associated to the particular window; LOCAL—the area where the local variables of a procedure are kept; LOW—the area which is used to transfer the parameters from the procedure associated with that window; GLOBAL—the area where the global variables are kept.

       Each procedure is assigned a bank.

       Extra procedures in main memory.

       Each parameter is assigned a field.

       Extra parameters in main memory.

Register banks are overlapped.

Squencing of banks is assigned at execution-time

(not in compile-time).

Figure 6.13. Logical organization of the memory with partially overlapping windows: proc A, B, C—procedures A, B, C.

Figure 6.14. Physical organization of the register file with partially overlapping windows: CWP—Current Window Pointer—the contents of this register impacts with execution of call and return; SWP—Saved Window Pointer—the contents of this register points to the position of the window that has been saved in the main store, by the operating system subroutine save. Symbols  (, 1, 2, 3, 4, 5, 6, 7) refer to the overlapping windows. Symbols A, B, C, D, E, F, G, H refer to various procedures. Symbol GLOBAL refers to registers R0–R9.

How many frames to move on overflow/underflow?

ONE (Tamir and Sequin).

Figure 6.15. An evaluation of the UCB-RISC instruction set: normalized execution times for the five standard procedureless EDN benchmarks, written in C and assembler.

2. Clock length: shorter

      32-bit microprocessor

      34-bit ALU (overflow detection)

      Sixteen 32-bit registers

      Barrel shifter with byte insert/extract

Pipelining:

      5 stages

      All stages executed by all machine instuctions

      All stages of the same length

      No hardwere interlock

      Pipeline hazards explicitely visible to the compiler

Hardwere support for the Booth step:

      32-bit multiplication

      18-cycles

      9-instructions

No sticky condition codes

Word addressing

Pipeline interlocks in software

Load/store architecture

Compiler can increase performance

by maximizing the amount of operands found in registers.

Addressing modes require at most one ALU operation.

Efficient support for 8-bit constans

Architectural support for system issues

Delayed branch (as in UCB-RISC or IBM 801)