Optimal memory pipelining depends on the ratio of off-chip and on-chip delays, plus many other factors. Therefore, precise input from DP and CD people was crucial. Unfortunately, these data were not quite known at the design time, and some solutions (e.g. PC-stack) had to work for various levels of the pipeline depth.

One group of latency stages (WAIT) was associated to instruction fetch; the other group was associated to operand load.

ALU

LOAD/STORE

BRANCH

COPROCESSOR