Compilation

a)

b)

Figure 7.6. Comparison of GaAs and silicon. Symbols CL and RC refer to the basic adder types (carry look ahead and ripple carry). Symbol B refers to the word size.

Figure 7.7. Comparison of GaAs and silicon technologies: an example of the bit-serial adder. All symbols have their standard meanings.

a)

b)

Figure 7.8. Comparison of GaAs and silicon technologies: design of the register cell: (a) an example of the register cell frequently used in the silicon technology; (b) an example of the register cell frequently used in the GaAs microprocessors. Symbol BL refers to the unique bit line in the four-transistor cell. Symbols A BUS and B BUS refer to the double bit lines in the seven-transistor cell. Symbol F refers to the refresh input. All other symbols have their standard meanings.

a)

b)

Figure 7.9. Comparison of GaAs and silicon technologies: pipeline design—a possible design error: (a) two-stage pipeline typical of some silicon microprocessors; (b) the same two-stage pipeline when the off-chip delays are three times longer than on-chip delays (the off-chip delays are the same as in the silicon version). Symbols IF and DP refer to the instruction fetch and the ALU cycle (datapath). Symbol T refers to time.

a1) IM or MP

a2) IM

a3) MP

b) IP

Figure 7.10. Comparison of GaAs and silicon technologies: pipeline design—possible solutions; (a1) timing diagrams of a pipeline based on the IM (interleaved memory) or the MP (memory pipelining); (a2) a system based on the IM approach; (a3) a system based on the MP approach; (b) timing diagram of the pipeline based on the IP (instruction packing) approach. Symbols P, M, and MM refer to the processor, the memory, and the memory module. The other symbols were defined earlier

1. Core-MIPS translators
MC680x0+1750A

2. Compilers
   C + Pascal + Ada
   

1. No NAND gates.
2. NOR gates can have up to 5 inputs, plus a 2-input AND on each of the 5 inputs.
   

1. Power Levels: High, Reference, and Low:

1. Circuits are always drawing current, and the number of such circuits on a die is severely limited, due to power consumption.
2. If smaller-size device are used, the circuit`s internal impedance becomes higher, it needs lwss power to operate, the number of circuits on a die increases, but the fun–out gets severely limited.
3. Three different circuits` types exit in the standard cell library. These represent the trade-offs between power, area, and fanout.

1. One can not utilize phantom logic on the chip, to implement
   functions like WIRED-OR (all outputs active). Circuits
   have a low “operating noise margin”.
2. One can not use three-state logic on the chip, to implement functions like MULTIPLE-SOURCE-BUS (only the output active). Circuits have no “off-state”.
3. Actually, if one insist on having a MULTIPLE-SOURCE- BUS on the chip, one can have it at the cost of only one active load and the need to precharge (both mean “constraints” and “slowdown on the architecture level).
4. Fortunately, logic function AND-OR is exactly what is needed to create a multiplexer - a perfect replacement for a bus.
5. Consequently, in hand-crafted areas (register file and barrel shifter), busses were used (no need for multiple active loads, and time was not critical). In standard-cell areas (all the rest) multiplexers were used.
6. Using multiplexers frequently resulted in extra functionality on the architecture level, simply because it was cheaper to keep them, than to exclude them.

a)

b)

a)

b)