This research has been sponsored by RCA

and conducted in collaboration with

the RCA Advanced Technology Laboratories,

Moorestown, New Jersey.

For the same power consumption,
at least half order of magnitude faster than Silicon.

Efficient integration of electronics and optics.

Tolerant of temperature variations.
Operating range: [- 200° C, + 200° C].

Radiation hard.
Several orders of magnitude more than Silicon.
[>100 million RADs].

(1) High density of wafer dislocations ® Low Yield ®
® Small chip size ® Low transistor count.

(2) Noise margin not as good as in Silicon. ®
® Area has to be traded in for higher reliability.

(3) At least two orders of magnitude
more expensive than Silicon.

(4) Currently having problems
with high-speed test equipment.

(1) Small area and low transistor count
(* in general, implications of this fact are dependent on
the speed of the technology *)

(2) High ratio of off-chip and on-chip delays
(* consequently, off-chip and on-chip delays access is
much longer then on-chip memory access *)

(3) Limited fan-in and fan-out (?)
(* temporary differences *)

(4) High demand on efficient fault-tolerance (?)
(* to improve the yield for bigger chips *)

Bipolar (TI + CDC)

JFET (McDAC)

GaAs MESFET Logic Families (TriQuint + RCA)

E-MESFET

Figure 7.2. Comparison (conservative) of GaAs and silicon, in terms of complexity and speed of the chips (assuming equal dissipation). Symbols T and R refer to the transistors and the resistors, respectively. Data on silicon ECL technology complexity includes the transistor count increased for the resistor count.

Figure 7.3. Comparison of GaAs and silicon, in the case of actual 32-bit microprocessor implementations (courtesy of RCA). The impossibility of implementing “phantom” logic (wired-OR) is a consequence of the low noise immunity of GaAs circuits (± 200 mV).

Figure 7.4. Processor organization based on the BS (bit-slice) components. The meaning of symbols is as follows: IN—input, BUFF—buffer, MUX—multiplexer, DEC—decoder, L—latch, OUT—output. The remaining symbols are standard.

Figure 7.5. Processor organization based on the FS (function slice) components: IM—instruction memory, I_D_U—instruction decode unit, DM_I/O_U—data memory input/output unit, DM—data memory.

Only a single-chip reduced architecture makes sense!

In Silicon environment,
we can argue: “RISC” or “CISC”.

In GaAs environment,
there is only one choice: “RISC”.

However, the RISC concept has to be
significantly modified for efficient GaAs utilization.

Assume a 10:1 advantage in on-chip switching speed, but
only a 3:1 advantage in off-chip/off-package memory access.

Will the microprocessor be 10 times faster?

Or only 3 times faster?

Why the Information Bandwidth Problem?

The Reduced Philosophy:

• Large register file
• Most or all on-chip memory is used for the register file
• On chip instruction cache is out of question
• Instruction fetch must be from an off-chip environment