Phases of a Well-Structured VLSI Design

 

  1. Generation of candidate architectures

    2. with approximately the same VLSI area.

  2. Comparison of candidate architectures,

    3. from the point of view of the compiled HLL code speed.

  3. Selection of one candidate architecture,

    4. and finalization of its schematics.

  4. Design of the VLSI chip:
    1. Schematic capture
    2. Logic and timing testing
    3. Placement and routing

5. Generation of the mask.

6. Chip fabrication, etc...

 

 

Typical Development Phases for

One 32-bit Microprocessor on a VLSI Chip

 

(or about the development of

DARPA's 32-bit RISC MIPS processors in GaAs and silicon)

 

  1. Announcement of project requirements

(on 1.1.1984.)

a. Type of the architecture (SU-MIPS)

b. Maximal on-chip transistor count

(30K)

c. Detailed specification of the

assembly language (Core-MIPS)

d. A set of benchmark programs typical

of the end-user application (13)

Three competitors selected by 12.13.1984.

    1. McDonell Douglas
    2. CDC + TI
    3. RCA (Purdue + TriQuint)

 

2. In-house research by the three competitors

(till 12.31.1985.)
  1. Generation of several candidate

    2. architectures under 30K transistors.

  2. Design of an ENDOT (isp') simulator

    3. all candidate architectures

    (why isp'?).

  3. All candidate architectures are

    4. ranked according to the above

    mentioned benchmark programs.

  4. Reasons for high/low ranking of

    5. specific candidate architectures

    are analysed, and the best candidate

    architectures are modified

    to become better. The final

    architecture is determined and

    "frozen" after several iterations.

  5. Detailed RTL design is completed,

and it is proven that

the total transistor count is below 30K.

 

3.Decision-making at the sponsor side

(by 1.1.1986.)
    1. Final architectures of all competitors are ranked (using the isp' simulators and the initially provided benchmarks).
    2. A subset of competitors is selected for further financing; others are offered to stay in the competition with the own financing.
    3. All those that stay in competition are shown all reports generated (by others) till that point.

 

4. In-house development

by the three competitors (till 12.31.1986.)

a. Improvements are added, after the solutions of the competition are reviewed, and their impact is verified with isp' simulations.

b. The architecture is frozen, forever.

c. The RTL design is redone, and frozen.

d. The appropriate semi-custom standard- cell family is selected, and the gate level design is completed. The standard-cell family choices, in the project which is the subject of this presentation:

The 1 micron E/D-MESFET GaAs

The 1.25 micron SOS-CMOS Si
  1. The completed gate level (GTL) design contains only the elements of the cells from the selected family (which includes the input, output, and input/output pads).

    2.  

  2. The gate level design is entered into a computer, using one of the following methods:

Graphic entry

HDL based entry

Logic equation entry

State machine entry

Direct entry of the net-list,

using a text editor

Except in the last case, the net list (needed for further work) is obtained using the appropriate translator.

  1. The net-list is tested (logic and timing), using an appopriate testing program (LOGSIM). If errors, the work iterates back, as needed.

    2.  

  2. The net-list is treated by an appropriate placement and routing program (MP2D). No timing errors (guaranteed) after the chip is fabricated! Logic errors possible after the chip is fabricated. The major two output files:

Artwork file for visual analysis

(for printer or ploter)

Fab file (for shipment to a chip

foundary, by regular mail or email)

At the chip foundary, the tab file is analysed, and each standard cell is substituted with its full-custom equivalent (details are typically confidental).

 

5. Further narrowing down of the sponsored competition, and widening up of the support technology (by 1.1.1987.)

  1. Only a subset of the sponsored competition is given further support for fabrication of a prototype at a lower-than-nominal speed.
  2. More funding made available for R&D in both, semiconductor and packaging tehnologies.
  3. More funding made available for the Core-MIPS translators (for the MC680x0 and the 1750A assembly languages) and compilers (for ADA and C).

 

6. Prototype fabrication (by 12.31.1987.)

7. Zero series at a still-lower-than-nominal speed (by 12.31.1988.)

8. Commercial series at the nominal speed (by 12.31.1989.)

9. The US eplogue!

10. The rest-of-the-world epilogue!

back to front page