The Fura RISC CPU

 

Word length: 32 bits

Registers: sixteen 32-bit

Execution model: register-to-register

dp = register_read -> ALU_operation -> register_write

Memory access: load & store

Pipelining:

delayed branching!!!

delayed loading!

Instruction classes:

1. ALU class

2. branch class

3. data memory class

4. system class

Instruction cycles:
    1. INSTRUCTION FETCH (IF)
    2. INSTRUCTION DECODING
    3. AND EXECUTION (IDX)
    4. DATA LOAD (LD)

 

Possible isp' coding window positionings

(i+1 is the current instruction)

 

 

Instruction count: 24 (or 16)

Instruction format:

  

ALU Class:

Add

a. ADD Rd, Rs1, Rs2

b. ADD Rd, Rs1, imm16

c. ADD Rd, PC, imm16 !

Substract

a. SUB Rd, Rs1, Rs2

b. SUB Rd, Rs1, imm16

c. SUB Rd, PC, imm16

 

Move

a. MOV Rd, Rs1

b. MOV Rd, imm16

c. MOV Rd, PC

 

Negate

a. NEG Rd, Rs1

 

Logical Not

a. LNOT Rd, Rs1

 

Logical And

a. LAND Rd, Rs1, Rs2

b. LADD Rd, Rs1, imm16

 

Logical Or

a. LOR Rd, Rs1, Rs2

b. LOR Rd, Rs1, imm1

 

Arithmetic Shift Left

  1. SLA Rd, Rs1, imm5

 

Arithmetic Shift Right

  1. SRA Rd, Rs1, imm5

 

Set if Equal

a. SEQ Rd, Rs1, Rs2

 

Set if Greater Than

a. SGT Rd, Rs1, Rs2

 

 

Branch Class:

 

Branch on True

a. BT Rd, Rs1

 

Branch Always

a. BA Rd

 

 

Data Memory Class:

 

- load & store instructions

load:

1. three cycles: IF, IDX & LD

2. IDX:

register_read - ALU_operation - output_latch_write (address)

3. LD

 

Load

a. SEQ Rd, Rs1, Rs2

store:

1. two cycles: IF & IDX

2. IDX:

register_read - ALU_operation - output_latch_write (data & data address)

Store

a. ST Rd, Rs2

 

 

System instructions:

Noophalt

  1. NOOPHALT

idle state of the machine; this instruction may be used

for filling slot(s) behind branches and/or loads,

or for real-time isp' programming,

or to support modular isp' programming.

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