vm@etf.rs

• IMP, Belgrade, Serbia, Yugoslavia (mid 70s)
• Data modem for HF radio in WTU networks
• Transmitter design: SAF
• Receiver design: DFT
• Source: [Milutinovic78] Milutinovic, V.,
  "Personal Notes in Microprocessor-Based Modem Design,"
  Technical Report, Michael Pupin Institute,
  Belgrade, Serbia, Yugoslavia, December 1978.

• Example: A 2400 b/s CCITT V.26/A Data Modem

Figure X1: Correspondence between dibit values and phase changes (source: [Milutinovic78]).

Legend:

dP—phase difference.

• Discrete phase jumps: line signal spectrum is too wide
• Solution: adjacent dibits are processed in two different channels,
  weighted with a rised-cosine envelope,
  and superimposed to give a line signal w/o discontinuities

a)

b)

Figure X2: Line signal, a) formula, b) waveform (source: [Milutinovic78]).

Legend:

T_E—envelope interval.

• If overlapping of adjacent signals is 50% of the time:
  width of the line signal spectrum is telephone channel compatible

Figure X3: Line signal spectrum (source: [Milutinovic78]).

Legend:

f—frequency,

G(f ⁺)/G_max(f ⁺)—normalized signal spectrum.

• If carrier frequency equals 1800Hz:
  about 99% of the spectrum is from 800Hz to 2800Hz
• Sampling rate:
  5600Hz
• In practice:
  sampling rate has to be higher than the theoretical minimum (e.g., 9600b/s)
• Ratio of sampling rate and carrier frequency is an integer (6):
  only 4 different signal shapes (good for lookup table implementations)
• If sampling rate equals 9600b/s
  each channel symbol is represented with 16 samples (4 zero samples)

Figure X4: Line signal samples (source: [Milutinovic78]).

Legend:

P₀—initial phase.

• Hardware: MP(8B) + ROM(2C) + PORT(8212) + D/A(8B) + LPF(RC)
• Software: Superimposing
  early samples of the later channel signal and
  later samples of the early channel signal

According to [Helstrom68],
the probability of correct detection (Q_d) of the phase (y ) of the signal s(t; y ) with unknown phase,
and buried in Gaussian noise with flat power density (N₀ = 1) is given by:

Provided the above conditions are satisfied,
the impulse responses h(t) of 4 filters matched to the signals
s(t; y ); y  = 0° , + 90° , + 180° , and + 270° are given by:

Figure X5: Theoretical foundations of statistical signal detection (source: [Milutinovic78]).

Legend:

y —signal phase,

s(t, y )—signal which is to be detected.

• If the least expensive microprocessors are slow for convolution:
  binary matched filtering (BMF) can be used
• BMF is best applied during the non-overlapping time intervals (NTI):
  middle T_D/2 interval of each dibit interval T_D
• Signs of M>=4 samples from the NTI define uniquely
  the current phase of the line signal

Figure X6: Correspondence between sample signs and initial phase of the line signal
(source: [Milutinovic78]).

Legend:

P₀—initial phase.

• BMF is a majority logic based CASE function:
  values of sampling instants can be optimized, to maximize SNR

Figure X7: Optimum sampling instants for maximal signal to noise ratio
(source: [Milutinovic78]).

Legend:

T_E—envelope interval.

Figure X8: Maximum likelihood function with noise (source: [Milutinovic78]).

Legend:

T_E—envelope interval.

• Hardware: HardLimiter(ThreeStateComparator) + MP
• Software: Interrupt(SynchroUnit) + PROM(1K)
• Important: The entire system fits into a chip

Figure X9: System structure (source: [Milutinovic78]).

Legend:

SU—synchronization unit,

L1/2—latches,

TB/C—tristate buffers,

I—interpolator.

Figure X10: Structure of a 4800 b/s CCITT compatible modem (source: [Milutinovic78]).

Legend:

TI—terminal interface,

Sc—scrambler,

Cod—coder,

Mod—modulator,

DAC—digital to analog converter,

IF—interpolating filter,

LI—line interface,

AGC—automatic gain control,

BPF—band pass filter,

StEq—statistical equalizer,

ADC—analog to digital converter,

Dem—demodulator,

Det&Dec—detector and decoder,

TE—timing extractor,

Desc—descrambler,

{a_i}—input data stream,

{b_i}—scrambled data stream,

S[t]—line signal.

Figure X11: Scrambler Structure (source: [Milutinovic78]).

Legend:

{a_i}—input data stream,

{b_i}—output data stream,

Figure X12: The CCITT V.27 coding scheme implemented in the modem under consideration
(source: [Milutinovic78]).

Legend: Self-explanatory.

Figure X13: Two components making the line signal (source: [Milutinovic78]).

Legend:

Figure X14: Analysis of the line signal (source: [Milutinovic78]).

Legend: Self-explanatory.

Figure X15: Memory organization of the transmitter design (source: [Milutinovic78]).

Legend:

• Transmitter hardware: no RAM, basic clock 320.5 ns (3.12MHz=650*4.8kHz)
• Clock: 1950 basic clock intervals in one signaling interval (1600Hz)
• Input port wiring: only 8 different bit combinations can occur
• Straps for CCITT V.27 coding: AD + BE + CF
• Output port interface: offset binary number system

Figure X16: Transmitter structure (source: [Milutinovic78]).

Legend:

MSB—the most significant bit,

LSB—the least significant bit,

RTS—request-to-send,

S(t)—line signal,

S_A(t)—zero-order polynomial-based approximation of the line signal,

T—bit interval,

S_s—synchronization switch (S_s = ON: modem master; S_s = OFF: terminal master),

S/P—serial-to-parallel converter,

IF—second-order low-pass filter as interpolating filter,

DAC—eight-bit digital-to-analog converter,

R—appropriate resistor.

Figure X17: Flow chart of the transmitter initialization code. (source: [Milutinovic78]).

Legend:

DAC—Digital-to-Analog Converter.

Figure X18: Flow chart of the transmitter operation code (source: [Milutinovic78]).

Legend:

DAC—Digital-to-Analog Converter.

Figure X19: Symbolics of the detection process (source: [Milutinovic78]).

Legend:

qF —previous signal in "quasiphase,"

qQ—previous signal in "quasiquadrature,"

F —inphase projection of current signal,

Q—quadrature projection of current signal,

sign Q—first bit to occur at the receiver output,

sign F —second bit to occur at the receiver output,

logical value of —third bit to occur at the receiver output,

TRUE ®  bit 1,

FALSE ®  bit 0.

After the formation of quantities F and Q,
sign Q is the first bit to be sent from the modem receiver,
followed by sign F ,
and bit ‘0’ finally, as the third bit, if is false, or bit ‘1’ if is true.
Phase and quadrature projections of the signal are formed as

Figure X20: Mathematics of the detection process (source: [Milutinovic78]).

Legend:

Figure X21: Clocking of the detection process (source: [Milutinovic78]).

Legend:

T_c—carrier period,

T_baud—Baud period,

T_s—sampling period,

t_A, t_B—symbol limits,

t₁, t₂, t₃, t₄—nominal sampling instants.

Figure X22: Sampling of the detection process (source: [Milutinovic78]).

Legend:

—overlapping interval,

—overlapping-free interval (when envelope shaping is present),

Column A—direct signal with different initial phases,

Column B—direct signal with j = 0 after propagation through phase shifters,

T_S—sampling period,

T_B—signaling interval,

T_C—carrier period.

(3)

(4)

(5)

(6)

So, if sign Q = 0 is sent to the terminal first, sign F  = 1 second, and bit ‘1’ (since ) last, the receiver output will correspond to the transmitter input, i.e. tribit 011.
If envelope shaping is introduced, the first and the fourth product in expressions (5) and (6)
are decreased relative to the second and third, and nothing else is changed.

Figure X23: Numerics of the detection process (source: [Milutinovic78]).

Legend: Self-explanatory.

• If jitter smaller than 8.33% of the signaling interval
  or interrupt request delay smaller than 16.66% of the signaling interval:
  signF and signQ remain unchanged
• If microprocessor clock equals 3.12MHz:
  the first sample is 325 cycles away from the signaling interval beginning;
  line signal samples are at 433 1/3 cycles apart

Figure X24: Hardware for the detection process (source: [Milutinovic78]).

Legend:

P1, P2, P3—input ports,

P4—output port,

M1, M2—multiplier inputs,

M3—high-order byte of the multiplier output,

S&H—sample-and-hold circuit,

AD—analog-to-digital converter,

CL—control logic generating support signals for S&H and AD,

 —chip-select signal for port P1,

F 2TTL—basic microprocessor clock: 3.12 MHz,

S/ —control signal for S&H circuits,

SOC—control signal for ADs,

MSB—the most significant bit,

P/S—parallel-to-serial converter,

PhSh—analog phase-shift circuit,

NOTE: the propagation time through all phase-shift circuits must be the same.

Figure X25: Memory organization of the receiver design (source: [Milutinovic78]).

Legend:

INIC—initialization routine,

REC—main program in the receiver,

SAMP—memory space for "old" and "new" envelope samples,

Figure X26: Flow chart of the receiver initialization code (source: [Milutinovic78]).

Legend: Self-explanatory.

Figure X27: Timing of the receiver code (source: [Milutinovic78]).

Legend:

REC—time interval covered by the main program in the receiver,

HALT—time interval when the processor is in the halt state,

t_a, t_b—limits of the signaling interval,

t₁, t₂, t₃, t₄—sampling instants.

Figure X28: Flow chart of the receiver operation code (source: [Milutinovic78]).

Legend:

SM—Signed Magnitude,

COB—Complementary Offset Binary.

Figure X29: Impact of the Gaussian noise (source: [Milutinovic78]).

Legend:

m.f.—optimum matched filter,

m.m.f.—modified matched filter, i.e., the approach under consideration here,

Pe —probability of error,

s _B—variance of the bandlimited Gaussian noise.

Figure X30: Impact of the quantization noise (source: [Milutinovic78]).

Legend:

Pe —error probability,

j—jitter in percent of the signaling interval time,

ADC—analog-to-digital converter.

• An MISD architecture for DFT

Symbols , and ,
refer to subchannel carrier frequency and its initial phase, respectively.
After being corrupted by multiplicative and additive disturbances,
the signal received is decomposed on the basis of mutual orthogonality of subsignals
over the middle T₀ portion of the signaling interval.
The frame is reconstructed according to the signs of F _n,k and Q_n,k, where

Finally, the phase difference between the received signal carrier (f _n,k)
and the local oscillator (f _n,k- 1) is measured and the local oscillator phase is updated
in all subchannels in order to meet differentially coherent detection requirements.
Measuring accuracy of 2.8125° proves to be satisfactory.

Figure X31: Mathematics of the HF data modem signal forming and detection
(source: [Milutinovic78]).

Legend: Self-explanatory.

Figure X32: Structure of the receiver (source: [Milutinovic78]).

Legend:

{a_k} transmitting bit stream k = 0, 1, …,

{b_k} receiving bit stream k = 0, 1, …,

C( f, t) fading channel transfer function,

n(t) additive noise,

T.E. timing extraction,

DPL digital phase locking,

OSC crystal oscillator,

AGC automatic gain control,

AFC Doppler effect correction,

  75 Hz clock with phase locked to the incoming signal frame transitions,

  2400 Hz clock synchronized with  .

Figure X33: Structure of the detector (source: [Milutinovic78]).

Legend:

PO—output port,

PI—input port.

Figure X34: The detection formula (source: [Milutinovic78]).

Legend: Self-explanatory.

Figure X35: Timing of the receiver code (source: [Milutinovic78]).

Legend: Self-explanatory.

Figure X36: Number of bits required in representation of final F _n,k and Q_n,k
for various values of the limitation factor L (source: [Milutinovic78]).

Legend: Self-explanatory.