The results/publications to follow are a direct or an indirect consequence of the industrial cooperation (R&D) listed here.
In all these cases, generated ideas resulted in new products or improvements of existing products.

PURDUE University Research Foundation, West Lafayette, Indiana:
6 R&D topics in computer architecture (1990+1991+1992+1993+1994+1995)

HAWAII University Research Foundation, Honolulu, Hawaii:
5 R&D topics in computer architecture (1990+1991+1992+1993+1994)

NCR Headquarters, Dayton, Ohio (and NCR Germany):
4 R&D topics in shared memory multiprocessing (1990+1991)
4 R&D topics in acceleration chips for multimedia PC (1991)

ENCORE Computer Systems, Fort Lauderdale, Florida (and ENCORE Massachusetts):
4 R&D topics in distributed shared memory for PC environment (1992+1993+1994)
4 R&D topics in reflective memory multiprocessing (1996)

TD Technology, Cleveland, Ohio (and MARUBENI/UNISYS + NIHON/MITSUBISHI Japan):
1 R&D topic in modeling for HLL simulation (1992)
1 R&D topic in modeling for silicon compilation (1993+1994+1995+1996)

AT&T Headquarters, Murray Hill, New Jersey:
1 R&D topic in computer architecture (1994)

QSI in Santa Clara, California (and NEC Japan):
1 R&D topic in stochastic routing for ATM (1995)

ET Communications, San Francisco, California:
1 R&D topic in logic synthesis for silicon compilation (1996)

SUN Microsystems, Palo Alto, California:
1 R&D topic in cache memory (1996)

INTEL Corporation, Santa Clara, California:
1 R&D topic in cache memory (1996)

Papers from non-IEEE journals have not been listed here;
listed papers span the areas from advanced processor design and data communications/networking to cache consistency and distributed shared memory.

1. V. Milutinovic,
   "Mapping of Neural Networks onto the Honeycomb Architecture,"
   Proceedings of the IEEE, December 1989, pp. 1875–1878.
2. D. Gajski, V. Milutinovic, H. J. Siegel, B. Furht,
   "Tutorial on Computer Architecture" (2^nd printing),
   IEEE Computer Society Press, Los Alamitos, California, 1990 (an IEEE Computer Society best-seller of all times).
3. V. Milutinovic,
   "Tutorial on Microprogramming and Firmware Engineering,"
   IEEE Computer Society Press, Los Alamitos, California, 1990.
4. B. Perunicic, S. Lakhani, V. Milutinovic,
   "Stochastic Modeling and Analysis of Propagation Delays in GaAs Adders,"
   IEEE Transactions on Computers, Vol. 40, No. 1, January 1991, pp. 31-45.
5. V. Milutinovic, D. Fura, W. Helbig,
   "Pipeline Design Trade-offs in 32-bit Gallium Arsenide Microprocessor,"
   IEEE Transactions on Computers, Vol. 40, No. 11, November 1991, pp. 1214-1224.
6. V. Milutinovic, L. Hoevel,
   "Terminology Risks with the RISC Concept in the Risky RISC Arena,"
   IEEE Computer, Vol. 25, No. 1, January 1992 (Open Channel), pp. 136–137.
7. M. Tomasevic, V. Milutinovic,
   "Tutorial on the Cache Coherency Problem in Shared-Memory Multiprocessors: Hardware Solutions,"
   IEEE Computer Society Press, Los Alamitos, California, 1993.
8. M. Tomasevic, V. Milutinovic,
   "A Survey of Hardware Solutions for Maintenance of Cache Consistency in Shared Memory Multiprocessor Systems,"
   IEEE MICRO (Part #1), October 1994, pp. 52–59.
9. M. Tomasevic, V. Milutinovic,
   "A Survey of Hardware Solutions for Maintenance of Cache Consistency in Shared Memory Multiprocessor Systems,"
   IEEE MICRO (Part #2), December 1994, pp. 61–66.
10. V. Milutinovic, Z. Petkovic,
    "Processor Design Using Silicon Compilation: Ten Lessons Learned from a RISC Design,"
    IEEE Computer, Vol. 28, No. 3, March 1995 (Open Channel), pp. 120–121.
11. S. Savic, M. Tomasevic, V. Milutinovic,
    "RMS for PC,"
    Microprocessor Systems, December 1995, pp. 609-619.*
12. Ekmecic, I. Tartalja, V. Milutinovic,
    "A Taxonomy of Heterogeneous Computing,"
    IEEE Computer, Vol. 28, No. 12, December 1995, pp 68-70.
13. Tartalja, V. Milutinovic,
    "Tutorial on the Cache Coherency Problem in Shared-Memory Multiprocessors: Software Solutions,"
    IEEE Computer Society Press, Los Alamitos, California, 1996.
14. M. Tomasevic, V. Milutinovic,
    "The World Invalidate Protocol,"
    Microprocessor Systems, March 1996, pp. 3-16.*
15. Grujic, M. Tomasevic, V. Milutinovic,
    "A Simulation Study of Hardware DSM Approaches,"
    IEEE Parallel and Distributed Technology, Spring 1996, pp. 74–83.
16. D. Milutinovic, V. Milutinovic,
    "Mapping of Interconnection Networks for Parallel Processing onto the Sea-of-Gates VLSI,"
    IEEE Computer, Vol. 29, No. 6, June 1996, pp. 112–113.
17. J. Protic, M. Tomasevic, V. Milutinovic,
    "A Survey of Distributed Shared Memory: Concepts and Systems,"
    IEEE Parallel and Distributed Technology, Summer 1996, pp. 63–78.
18. Ekmecic, I. Tartalja, V. Milutinovic,
    "A Survey of Heterogeneous Computing: Concepts and Systems,"
    Proceedings of the IEEE, August 1996, pp. 1124–1144.
19. V. Milutinovic,
    "Surviving the Design of a 200MHz RISC Microprocessor: Lessons Learned,"
    IEEE Computer Society Press, Los Alamitos, California, 1996.
20. V. Milutinovic,
    "The Best Method for Presentation of Research Results,"
    IEEE TCCS Newsletter, September 1996, pp. 1-6.
21. V. Milutinovic,
    "Some Solutions for Critical Problems in the Theory and Practice of Distributed Shared Memory: New Ideas to Analyze,"
    IEEE TCCS Newsletter, September 1996, pp. 7-12.
22. Tartalja, V. Milutinovic,
    "A Survey of Software Solutions for Cache Consistency Maintenance in Shared Memory Multiprocessors,"
    IEEE Software, January 1997 (accepted).
23. J. Protic, M. Tomasevic, V. Milutinovic,
    "Tutorial on DSM: Concepts and Systems,"
    IEEE Computer Society Press, Los Alamitos, California, USA, 1997 (accepted).
24. D. Milicev, Z. Petkovic, D. Raskovic, D. Jelic, M. Jelisavcic, D. Stevanovic, A. Milenkovic, V. Milutinovic,
    "Modeling of Modern 32-bit and 64-bit Microprocessors,"
    IEEE Transactions on Education, 1997 (accepted).
25. Milutinovic, V.,
    "Surviving the Design of Microprocessor and Multimicroprocessor Systems: Lessons Learned,"
    IEEE Computer Society Press, Los Alamitos, California, USA, 1997 (accepted).
26. V. Milutinovic, B. Markovic, M. Tomasevic, M. Tremblay,
    "The Split Temporal/Spatial Cache Memory,"
    IEEE Transactions on Computers, 1997 (conditionally accepted).
    Conference version available from the Proceedings of the IEEE MELECON-96, Bari, Italy, May 1996, pp. 1108–1111.
27. Milutinovic, V.,
    "A Research Methodology in the Field of Computer Engineering for VLSI,"
    IEEE Transactions on Education, 1997 (conditionally accepted).
    Conference version available from the Proceedings of the IEEE MIEL-95, Nis, Serbia, Yugoslavia, pp. 811–816.
28. Ekmecic, I., Tartalja, I., Milutinovic, V.,
    "Tutorial on Heterogeneous Processing: Concepts and Systems,"
    IEEE Computer Society Press, Los Alamitos, California, USA, 1997 (conditionally accepted).
29. …
30. …

SCI—over 50 (excluding self-citations);

BOOKS (including textbooks, monographs, as well as M.Sc. and Ph.D. theses)—over 100;

INSPEC—over 1000.

This list includes all textbooks available at the Stanford University Bookstore and at the Purdue University Bookstore in Fall 1996
(only the textbooks published on or after 1990), which include the term Computer Architecture in their title (or subtitles),
and cover the general field of computer architecture.

Position X—position of VM in the ranking of referenced authors (s = shared position);

Y citations—number of VM citations in the textbook (na = not applicable).

Flynn, M. J., Computer Architecture, Jones and Bartlett, USA (96)
position 1 (12 citations)

Bartee, T. C., Computer Architecture and Logic Design, McGraw-Hill, USA (91)
position 1 (2 citations)

Tabak, D., RISC Systems (RISC Processor Architecture), Wiley, USA (91)
position 1s (6 citations)

Stallings, W., Reduced Instruction Set Computers (RISC Architecture), IEEE CS Press, Los Alamitos, California, USA (90)
position 1s (3 citations)

Heudin, J. C., Panetto, C., RISC Architectures, Chapman-Hall, London, England (92)
position 3s (2 citations)

van de Goor, A. J., Computer Architecture and Design, Addison Wesley, Reading, Massachusetts, USA (2^nd printing, 91)
position 4s (3 citations)

Tannenbaum, A., Structured Computer Organization (Advanced Computer Architecures), Prentice-Hall, USA (90)
position 5s (4 citations)

Feldman, J. M., Retter, C. T., Computer Architecture, McGraw-Hill, USA (94)
position 7s (2 citations)

Stallings, W., Computer Organization and Architecture, Prentice-Hall, USA (96)
position 9s (3 citations)

Murray, W., Computer and Digital System Architecture, Prentice-Hall, USA (90)
position >10s (2 citations)

Wilkinson, B., Computer Architecture, Prentice-Hall, USA (91)
position >10 (2 citations)

Decegama, A., The Technology of Parallel Processing (Parallel Processing Architectures), Prentice-Hall, USA (90)
position >10s (2 citations)

Baron, R. J., Higbie, L., Computer Architecture, Addison-Wesley, USA (92)
position >10s (1 citation)

Tabak, D., Advanced Microprocessors (Microcomputer Architecture), McGraw-Hill, USA (95)
position >10s (1 citation)

Zargham, M. R., Computer Architecture, Prentice-Hall, USA (96)
position >10s (1 citation)

Hennessy, J. L., Patterson, D. A., Computer Architecture: A Quantitative Approach, Morgan-Kaufmann, USA (96)
na (0 citations)

Hwang, K., Advanced Computer Architecture, McGraw-Hill, USA (93)
na (0 citations)

Kain, K., Computer Architecture, Addison-Wesley, USA (95)
na (0 citations)