FOREWORD

PREFACE

ACKNOWLEDGMENTS

AN INTRODUCTION TO RISC PROCESSOR ARCHITECTURE FOR VLSI

1.1   THE GOAL OF THIS BOOK
1.2   THE ON-BOARD COMPUTER FOR STAR WARS" PROJECT

2   AN INTRODUCTION TO RISC DESIGN METHODOLOGY FOR VLSI

2.1   BASIC STAGES OF A RISC PROCESSOR DESIGN FOR VLSI
2.2   TYPICAL DEVELOPMENT PHASES FOR A RISC MICROPROCESSOR
2.2.1   Request For Proposals
2.2.2   Choice of Contestants
2.2.3   Creating the Most Suitable Architecture
2.2.4   Comparison of the Contestants' Architectures
2.2.5   Final Architecture
2.2.6   Chip Fabrication and Software Environment

3   AN INTRODUCTION TO HARDWARE DESCRIPTION LANGUAGES

3.1   INTRODUCTION
3.2   ENDOT AND ISP'
3.2.1   Definition of the ISP' Program Declaration Section
3.2.2   Definition of the ISP' Program Behavior Section
3.2.3   Examples of ISP' Program Declaration and Behavior Section
3.2.4   Creating a .t File
3.2.5   Example of a .t File
3.2.6   Simulation
3.2.7   The .m File
3.2.8   The .i File
3.2.9   Example of MIPS for Star Wars Benchmark Programs
3.2.10   General Methodology of Computer System Performance Evaluation.
3.2.11   Natural and Synthetic Workloads
3.2.11.1   Synthetic Jobs
3.2.11.2   Benchmark Programs
3.2.12   Summary

4   AN INTRODUCTION TO VLSI

4.1   THE BASICS OF VLSI CHIP DESIGN
4.1.1   A Classification of VLSI Design Methodologies
4.1.2   More on VLSI Classification
4.1.3   VLSI Design Activities
4.1.4   Basic Elements of VLSI Chip Design
4.1.5   Design and Fabrication Costs
4.2   THE VLSI DESIGN METHODOLOGIES
4.2.1   FC VLSI
4.2.1.1   FC VLSI Silicon Technology
4.2.1.2   FC VLSI GaAs Technology
4.2.2   SC VLSI
4.2.3   GA VLSI
4.2.4   PL VLSI
4.2.5   Summary of SC VLSI, GA VLSI, and PL VLSI.
4.2.6   ST VLSI

5   VLSI RISC PROCESSOR DESIGN

5.1   PREFABRICATION DESIGN
5.1.1   LOGSIM and Mandatory Files
5.1.1.1   The Imode.dat File
5.1.1.2   The gen4.dat File
5.1.1.3   The print.dat File
5.1.2   MP2D and Optional Files
5.1.3   Simulation
5.1.4   MP2D Placement and Routing Files
5.1.4.1   The mmode.dat File
5.1.4.2   The dmode.dat File
5.1.4.3   The drop.dat File
5.1.4.4   The title.dat File
5.1.5   The ARTWORK and FABRICATION Files
5.1.6   Summary
5.2 POSTFABRICATION TESTING
5.2.1   Test Vectors and Fault Coverage
5.2.1.1   The SSA Fault Model
5.2.1.2   Random Test Vector Generation
5.2 1.3   The SP and BIST Approaches for Sequential and Combinational Circuits
5.2.1.4   The SP Techniques
5.2.2   Testing Memory Chips
5.2.2.1   Testing ROM Memories
5.2.2.2   Testing RAM Memories
5.3   SUMMARY

6   RISC: THE ARCHITECTURE

6.1   RISC PROCESSOR DESIGN PHILOSOPHY.
6.1.1   The Technology Domain
6.1.2   The Application Domain
6.2   BASIC EXAMPLES: THE UCB-RISC
6.2.1   UCB-RISC Architecture
6.2.1.1   The Hardware Interlock
6.2.1.2   The Software Interlock
6.2.2   Determining Which Interlock to Use
6.2.3   Realization of the Pipeline in UCB-RISC I and UCB-RISC II
6.2.4   Instruction Format of the UCB-RISC
6.2.4.1   The Short Immediate Operand Format
6.2.4.2   The Long Immediate Operand Format
6.2.4.3   Other Instruction Aspects
6.2.5   The Load and Store Instructions
6.2.5.1   The Load Instructions
6.2.5.2   The Store Instructions
6.2.6   UCB-RISC Addressing Mode
6.2.7   UCB-RISC Register File Organization.
6.2.8   UCB-RISC Processor Test Results
6.3   BASIC EXAMPLES: THE SU-MIPS
6.3.1   Structure of SU-MIPS Pipeline
6.3.2   Performance Evaluation of SU-MIPS Processor. .
6.3.3   Definition of Various Hazards
6.3.3.1   Resource Hazards
6.3.3.2   Sequencing Hazards
6.3.3.3   Timing Hazards
6.3.4   Examples of Various SU-MIPS Processor Hazards
6.3.5   Code Optimization
6.3.5.1   The Basic Block
6.3.5.2   Three Code Relocation Schemes
6.3.5.3   Combinations of the Relocation Schemes
6.4   SUMMARY

7   RISC: SOME TECHNOLOGY-RELATED ASPECTS OF THE PROBLEM

7.1   IMPACTS OF NEW TECHNOLOGIES
7.1.1   Submicron Silicon Technology and Microprocessors
7.1.2   GaAs Technology
7.1.3   The Impact of GaAs Technology on Microprocessor Architecture
7.1.4   Comparative Values Between GaAs and Silicon
7.1.5   Basic Realization Strategy for GaAs Processors
7.1.6   RISC Architecture for GaAs
7.1.7   Applications of GaAs Processors
7.1.8   Differences Between GaAs and Silicon Microprocessors
7.1.9   Differences Between GaAs and Silicon Adder Design
7.1.10   Advanced Issues
7.1.10.1   Register File Design
7.1.10.2   Pipelining in GaAs Technology
7.1.10.3   Approaches to Datapath Utilization
7.1.11   Admonitions
7.2 GAAS RISC PROCESSORS: ANALYSIS OF A SPECIAL CASE
7.2.1   Technological Restrictions
7.2.2   Explanation of Appendix A
7.2.3   Lessons Learned and Catalytic Migration
7.3   SUMMARY

8   RISC: SOME APPLICATION-RELATED ASPECTS OF THE PROBLEM

8.1   THE N-RISC PROCESSOR ARCHITECTURE
8.2   THE ARCHITECTURE OF AN ACCELERATOR FOR NEURAL NETWORK ALGORITHMS
8.3   SUMMARY

9   SUMMARY

9.1   WHAT WAS DONE?
9.2   WHAT IS NEXT?
9.3   DOING YOUR OWN RESEARCH AND DEVELOPMENTS

10   REFERENCES AND SUGGESTED READING

10.1   REFERENCES
10.2   SUGGESTED READING
10.3   RECENT REFERENCES OF THE AUTHOR

APPENDIX A   A MODEL OF A SIMPLE RISC MICROPROCESSOR

APPENDIX B   AN EXPERIMENTAL 32-BIT RISC MICROPROCESSOR WITH A 200 MHz CLOCK

APPENDIX C   AN EXPERIMENTAL 64-BIT RISC MICROPROCESSOR ON OVER 2 MTR COMPLEXITY

APPENDIX D   A METHODOLOGY FOR NEW RESEARCH AND DEVELOPMENTS

APPENDIX E   ACRONYMS AND ABBREVIATIONS

APPENDIX F   SHORT BIOGRAPHICAL SKETCH OF THE AUTHOR

INDEX


Back